Integrated circuits can include an array of dynamic random access memory cells (DRAM). A DRAM cell includes a storage capacitor for storing a charge that represents, for example a logic “0” or “1”. Since the charge stored within the cell capacitor leaks due to parasitic current paths, the charge has to be refreshed periodically. The time between two refresh events of the same memory cell is called retention time. The retention time is set such that the storage capacitor has always enough charge so that it can be detected by a sense amplifier. A refresh operation is usually performed for a complete row of memory cells within the memory cell array. During a refresh cycle, the information stored in the memory cells of a row is read out, amplified, and written back into the memory cells. The size of a memory cell of a DRAM is small so that dynamic memories provide for a high cell count on a single chip. A refresh operation, however, is time-consuming and slows down the operation of a DRAM.
From the foregoing discussion, it is desirable to provide a refresh scheme which reduces the adverse impact to performance.